1. Field of the Invention
The present invention generally relates to a semiconductor memory device and a method of performing a data reduction test. More specifically, the present invention relates to a semiconductor memory device of a multi-chip package type that is designed to allow shortening the time for data reduction test or IO reduction test. The present invention further relates to a method of performing a data reduction text in a shortened time period.
Priority is claimed on Japanese Patent Application No. 2008-115828, filed Apr. 25, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, there has been progressed shrinkage of semiconductor package. For example, the thickness of the package has been on the reduction. The density of integration of the package has been on the increase. The demand for the multi-chip package has been on the increase. The multi-chip package is suitable for realizing the high density integration of the semiconductor memory device, wherein multiple chips are stacked.
The test for the multi-chip package is carried out by testing each chip separately. Increase the number of stacked chips in the multi-chip package will increase the time for the data reduction test. For the production cost to be reduced, there can be need to shorten the time for the data reduction test. A development for the method of shortening the test time is needed, while the number of stacked chips in the multi-chip package is increased in order to increase memory capacity.
Japanese Unexamined Patent Application, First Publication, No. 6-333400 discloses a synchronous semiconductor memory device that is designed to shorten test time for SDRAM. The synchronous semiconductor memory device is adapted to perform data reduction into one-bit data from the data stored in plural memory cells which are simultaneously selected. The synchronous semiconductor memory device is designed to perform test efficiently in a shorten time. However, the synchronous semiconductor memory device is not designed to shorten time for the data reduction test, and not to perform the data reduction test for plural stacked chips simultaneously. The synchronous semiconductor memory device is not designed to shorten the time for the data reduction test and to reduce the production cost.
Japanese Unexamined Patent Application, First Publication, No. 2000-40397 discloses a semiconductor memory device that is designed to perform a kind of IO reduction tests. The semiconductor memory device allows acquisition of redundancy relief address. The semiconductor memory device also allows interfering test between memory cells adjacent to each other. The semiconductor memory device is designed to reduce the chip size and shorten the test time. For performing IO test of the semiconductor memory device, plural bits being different in relief unit are reduced in the same reduction process to store the reduced data, and these plural bits in those relief units are also read out in the same IO reduction process, thereby shortening the test time. However, the semiconductor memory device is not designed to shorten time for the data reduction test, and not to perform the data reduction test for plural stacked chips simultaneously. The semiconductor memory device is not designed to shorten the time for the data reduction test and to reduce the production cost.
Japanese Unexamined Patent Application, First Publication, No. 2003-168299 discloses a memory circuit having data compression function. In the test, the memory circuit reduces the compression rate, while increasing the relief probability by relief cells. Further, the memory circuit allows a tester to perform simultaneous measurements for shortening the test time. However, the memory circuit is not designed to shorten time for the data reduction test, and not to perform the data reduction test for plural stacked chips simultaneously. The s memory circuit is not designed to shorten the time for the data reduction test and to reduce the production cost.